The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
FIG. 1A shows a traditional static random access memory (SRAM) cell in which a bi-stable feedback loop retains a single bit of information without having to be periodically refreshed, such as is necessary for a dynamic random access memory (DRAM). In standard six-transistor SRAM cells, an output of a first inverter 100 is connected to an input of a second inverter 104 while an output of the second inverter 104 is connected to an input of the first inverter 100. As long as power is supplied to the first and second inverters 100 and 104, the SRAM cell will retain the single bit of information.
Either the output of the first inverter 100 or the output of the second inverter 104 is considered to be the single bit of information. For example, a high voltage at the output of the second inverter 104 may correspond to a digital one while a low voltage at the output of the second inverter 104 may correspond to a digital zero. In order to change the state of the SRAM cell, the inputs to both the first and second inverters 100 and 104 are operated on by a bitline (BL) and an inverted bitline (also called bitline bar, or BLB), respectively. The bitline and inverted bitline apply signals to the first and second inverters 100 and 104 via pass gates 108 and 112, respectively. The pass gates 108 and 112 are controlled by a wordline and are implemented as n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), each including a gate terminal (“gate”), a drain terminal (“drain”), and a source terminal (“source”).
The schematics are drawn so that, for n-channel transistors, the source terminal is positioned below the drain terminal. Conversely, p-channel transistors, which each include a gate, a drain, and a source, are drawn so that the source terminal is positioned above the drain terminal. For horizontally-drawn transistors, both p-channel and n-channel, the source terminal is positioned to the left of the drain terminal.
In FIG. 1B, the first and second inverters 100 and 104 are shown to simply be two-transistor complementary metal-oxide-semiconductor (CMOS) inverters. The first inverter 100 includes an n-channel MOSFET (NMOS) 120 and a p-channel MOSFET (PMOS) 124 connected in series. The second inverter 104 includes an NMOS 128 and a PMOS 132 connected in series. Sources of the PMOS 124 and the PMOS 132 are connected to a first reference potential 136, such as VDD. Sources of the NMOS 120 and the NMOS 128 are connected to a second reference potential 140, such as VSS or ground.
FIGS. 2A-2D are graphical depictions of writing—i.e., changing the SRAM cell from one state to the other. In FIG. 2A, gates of the NMOS 120 and the PMOS 124 are “low” (i.e., at the second reference potential 140), which turns the PMOS 124 on (indicated with thicker lines) and the NMOS 120 off (indicated with broken lines). The PMOS 124 therefore holds a first node between the PMOS 124 and the NMOS 120 “high” (i.e., at the first reference potential 136).
As a result, the high voltage is applied to the gates of the PMOS 132 and the NMOS 128, turning on the NMOS 128 and turning off the PMOS 132. This causes a second node between the PMOS 132 and the NMOS 128 to be pulled low by the NMOS 128, which then feeds back to the gates of the PMOS 124 and the NMOS 120. To change the state of the SRAM cell, the bitline and the inverted bitline are driven to new values of high and low, respectively.
In FIG. 2B, the wordline is asserted, which turns on (or, enables) the pass gates 108 and 112. This connects the high voltage on the bitline to the low voltage at the gates of the NMOS 120 and the PMOS 124; in addition, the low voltage of the inverted bitline is connected to the high voltage at the gates of the NMOS 128 and the PMOS 132. As a result, the pass gate 112 attempts to pull the second node low while the PMOS 124 attempts to pull the second node high. Traditional SRAM cells are sized so that the pass gate 112 is stronger (i.e., being able to source or sink more current) than the PMOS 124. Write margin is primarily determined by the relative strengths of an NMOS pass gate and a PMOS. Pull up of the first node is primarily the result of pull down of the second node caused by the pass gate 112. Also, the NMOS 120 and the NMOS 128 are sized to be stronger than the pass gates 112 and 108 for stability reasons.
Similarly, if the opposite value were being written to the SRAM cell, the pass gate 108 would need to be stronger than the PMOS 132. Relative strengths may be determined by width-to-length ratios, with a higher width-to-length ratio meaning that the transistor is stronger. However, for a given width-to-length ratio, an NMOS may be stronger than a PMOS.
In FIG. 2C, assuming that the transistors are sized correctly, the first node is pulled high toward the bitline while the second node is pulled low towards the inverted bitline. This results in turning on the NMOS 120 and the PMOS 132 while turning off the NMOS 128 and PMOS 124. However, as voltage supplies (the difference between the first reference potential 136 and the second reference potential 140) decrease, manufacturing defects and process variations may cause some of the SRAM cells to fail to function adequately.
For example, in one or more SRAM cells of a memory chip, the nodes may not transition quickly enough in order for data to be latched repeatably at a desired clock speed. The chip may be binned to a lower clock speed, may be discarded, or may have a mechanism for avoiding using the underperforming cells. This reduces yield and therefore increases cost. In fact, the nodes may not transition at all regardless of clock speed if process variation is too great such that a PMOS is stronger than an NMOS pass gate.
In FIG. 2D, the wordline is de-asserted, and the NMOS 120 and the PMOS 132 maintain the voltages at the first and second nodes against any parasitic leakage.